Knowledge Engineering in First-order logic
In this page we will learn about What is knowledge-engineering?, The knowledge-engineering process, Identify the task, Assemble the relevant knowledge, Decide on vocabulary, Encode general knowledge about the domain, Encode a description of the problem instance, Pose queries to the inference procedure and get answers, Debug the knowledge base.
What is knowledge-engineering?
Knowledge engineering is the process of building a knowledge base in first-order logic. In knowledge engineering, a knowledge engineer is someone who researches a given domain, learns significant domain concepts, and develops a formal representation of the objects.
In this topic, we'll look at the knowledge engineering process in the context of an electronic circuit, which we're already familiar with. This method is best suited for developing specialized knowledge bases.
The knowledge-engineering process:
The knowledge-engineering process is broken down into the following steps. We will construct a knowledge foundation that will allow us to reason about the digital circuit (One-bit full adder) that is shown below using these techniques.
1. Identify the task:
The initial stage in the procedure is to determine the task, and there are several reasoning tasks for the digital circuit.
We'll look at the circuit's functionality at the highest level, or first level:
- Does the circuit add properly?
- What will be the output of gate A2, if all the inputs are high?
At the second level, we will inspect the circuit structure details such as:
- Which gate is connected to the first input terminal?
- Does the circuit have feedback loops?
2. Assemble the relevant knowledge:
In the second step, we will put together the necessary information for digital circuits. As a result, we need to know the following things about digital circuits:
- Wires and gates are used in logic circuits.
- The signal travels through wires to the gate's input terminal, and each gate produces an output that travels farther.
- There are four types of gates in this logic circuit: AND, OR, XOR, and NOT.
- There is one output terminal and two input terminals on each of these gates (except NOT gate, it has one input terminal).
3. Decide on vocabulary:
Selecting functions, predicates, and constants to represent circuits, terminals, signals, and gates is the next phase in the process. To begin, we'll separate the gates from one another and from other items. Each gate is represented as an object with a unique name, such as Gate(X1). ach gate's functionality is determined by its type, which is represented by constants such as AND, OR, XOR, and NOT. A predicate will be used to identify circuits: Circuit(C1).
For the terminal, we will use predicate: Terminal(x).
The function In(1, X1) will be used to denote the first input terminal of the gate, and Out(1, X1) will be used to denote the output terminal.
The connectivity between gates can be represented by predicate Connect(Out(1, X1), In(1, X1)).
We use a unary predicate On(t), which is true if the signal at a terminal is on.
4. Encode general knowledge about the domain:
We'll need the following principles to encode general information about logic circuits:
When two terminals are connected, the input signal is the
same, which can be represented as:
∀ t1, t2 Terminal (t1) ∧ Terminal (t2) ∧ Connect (t1, t2) → Signal (t1) = Signal (2).
Every terminal's signal will have a value of 0 or 1, and
will be represented as:
∀ t Terminal (t) →Signal (t) = 1 ∨Signal (t) = 0.
Connect predicates are commutative:
∀ t1, t2 Connect(t1, t2) → Connect (t2, t1).
Representation of types of gates:
g Gate(g) ∧ r = Type(g) → r = OR ∨r = AND ∨r = XOR ∨r = NOT.
If and only if any of the AND gate's inputs are 0, the
output will be zero.
g Gate(g) ∧ Type(g) = AND →Signal (Out(1, g))= 0 ⇔ ∃n Signal (In(n, g))= 0.
Output of OR gate is 1 if and only if any of its input is 1:
∀ g Gate(g) ∧ Type(g) = OR → Signal (Out(1, g))= 1 ⇔ ∃n Signal (In(n, g))= 1
Output of XOR gate is 1 if and only if its inputs are
∀ g Gate(g) ∧ Type(g) = XOR → Signal (Out(1, g)) = 1 ⇔ Signal (In(1, g)) ≠ Signal (In(2, g)).
Output of NOT gate is invert of its input:
∀ g Gate(g) ∧ Type(g) = NOT → Signal (In(1, g)) ≠ Signal (Out(1, g)).
- The gates in the circuit above all have two inputs and one output (except NOT gate).
∀ g Gate(g) ∧ Type(g) = NOT → Arity(g, 1, 1) ∀ g Gate(g) ∧ r =Type(g) ∧ (r= AND ∨r= OR ∨r= XOR) → Arity(g, 2, 1).
All gates are logic circuits:
∀ g Gate(g) → Circuit (g).
5. Encode a description of the problem instance:
Now, in order to decode the problem of circuit C1, we must first classify the circuit and its gate components. This phase is simple if the problem's ontology has already been considered. This step entails writing simple atomic sentences of idea instances, which is referred to as ontology.
We may encode the issue instance in atomic phrases for the given circuit C1 as follows:
Because there are two XOR gates, two AND gates, and one OR gate in the circuit, the atomic sentences for these gates will be:
For XOR gate: Type(x1)= XOR, Type(X2) = XOR For AND gate: Type(A1) = AND, Type(A2)= AND For OR gate: Type (O1) = OR.
And then represent the connections between all the gates.
Note: Ontology defines a particular theory of the nature of existence.
6. Pose queries to the inference procedure and get answers:
We'll find all of the possible values for all of the terminals in the adder circuit in this stage. The initial question will be:
What input combination should result in the first output of circuit C1 being 0 and the second output being 1?
∃ i1, i2, i3 Signal (In(1, C1))=i1 ∧ Signal (In(2, C1))=i2 ∧ Signal (In(3, C1))= i3 ∧ Signal (Out(1, C1)) =0 ∧ Signal (Out(2, C1))=1
7. Debug the knowledge base:
We'll now debug the knowledge base, which is the final step in the process. In this stage, we'll try to figure out what's wrong with the knowledge base.
We may have missed statements like 1≠ 0 in the knowledge base.